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The differential decoding process is equally simple to implement using a second exclusive-or gate and a 1-bit delay. The task is to observe whether the detected data stream changes state over consecutive bits, in which case a logic 1 must have been present in the input. If there is no change of state, a logic 0 must have been sent. This change of state information is unaffected by any data inversion and hence the encoding/decoding process is foolproof against carrier recovery phase ambiguity. | ![]() |